Project Overview

Our project aims to build and silicon-prove a chip framework that will support a continuous cycle of chip designs, or “tape outs,” ready for fabrication. The project’s overall goal is to give interested students experience in chip design and fabrication. The framework we design will provide space for multiple small projects and the ability to run each independently. The project modules will be created by a co-curricular team of students ranging from freshmen to seniors. By breaking the design process into smaller, less complex subprojects, students will be able to complete modules within a semester. Each module will be fabricated and synthesized as a hard macro that can be used in our framework.

The chip framework will integrate the modules into a unified ASIC by connecting each module to the chip’s GPIOs and management wrapper, or microcontroller. All of the chip’s resources will be multiplexed between the different projects, depending on which is active at the time. The design process will involve creating a chip layout and fully-functional management core, as well as configuration scripting, Verilog coding, and C programming. The users of our project will be the students designing the modules and participating in the ISU Chip Fab Co-Curricular team. They will be familiar with the project’s purpose, setup, and tools. Once completed, the chip framework will allow the students to have their designs fully implemented and synthesized.